1. Field of the Invention
The invention relates generally to field effect devices. More particularly, the invention is related to field effect devices with enhanced performance.
2. Description of the Related Art
Field effect devices, such as field effect transistors, are commonly used in semiconductor circuits. Field effect transistors find such common use due to a low power consumption, a relative ease of fabrication of field effect transistors, and a relative ease in scaling of field effect transistors.
While field effect transistors are readily fabricated and readily scaled to increasingly smaller dimensions, field effect transistors when scaled to increasingly smaller dimensions are nonetheless not entirely without problems. In particular, field effect transistors when scaled to increasingly smaller dimensions are often susceptible to short channel effects (SCEs). Short channel effects are electrical effects that are manifested when a gate electrode partially or completely loses electrical control over a channel region within a semiconductor substrate. Such loss of control of a gate electrode over a channel region increases as a channel length is scaled down.
One method that may be used to control an SCE is to use an ultra thin semiconductor-on-insulator (UT-SOI) structure in the channel area of a MOSFET. However, the mobilities of charge carriers in UT-SOI are degraded. In turn, the charge carrier mobility degradation causes an undesirable degradation of device performance. Therefore, desirable are MOSFET structures that may possess UT-SOI channel dimensions (to obtain good control of SCE) while simultaneously maintaining acceptable carrier mobility and desirable performance.
Various semiconductor structures having desirable properties, and methods for fabrication thereof, are known in the semiconductor fabrication art.
For example, Doris et al., in U.S. Pub. No. 2006/0001095, teaches a method for fabricating a field effect transistor within an ultra-thin semiconductor-on-insulator substrate in a fashion that minimizes a threshold voltage variation of the field effect transistor. To achieve the foregoing result, this particular method includes varying a semiconductor-on-insulator thickness in conjunction with a variation of gate length within the field effect transistor.
In addition, Zhu et al., in U.S. Pub. No. 2005/0090066 and U.S. Pat. No. 6,939,751, teaches a field effect transistor structure comprising a raised source/drain region fabricated with enhanced epitaxial control. To achieve the foregoing result, this particular field effect transistor structure uses a silicon-germanium alloy layer over a silicon layer when fabricating the raised source/drain region.
Further, Chen et al., in U.S. Pat. No. 6,924,517, teaches a field effect transistor structure fabricated within an ultra-thin semiconductor-on-insulator substrate to provide the field effect transistor with enhanced performance. This particular field effect transistor structure realizes the foregoing object by using a comparatively thin channel region that separates source/drain regions that are recessed to a depth greater than the comparatively thin channel region.
Still further, Doris et al., in U.S. Pat. No. 6,914,303, teaches a method for fabricating an ultra-thin channel metal oxide semiconductor field effect transistor with a decreased channel resistance and a decreased thermal budget. This particular method realizes the foregoing objects by using multiply offset spacer layers when fabricating the metal oxide semiconductor field effect transistor.
Yet further, Wu, in U.S. Pat. No. 6,117,712, teaches a method for fabricating a field effect transistor on a semiconductor-on-insulator substrate to provide the field effect transistor with an ultra-short channel. The particularly disclosed method includes use of a high permittivity dielectric material layer.
Finally, Maszara, in U.S. Pat. No. 5,250,454 teaches a method for forming a raised source/drain region within a field effect transistor device. This particular method uses epitaxial recrystallization of an amorphous semiconductor material layer formed upon a monocrystalline non-raised source/drain region.
Semiconductor structure and device dimensions are certain to continue to decrease, and as a result thereof desirable are semiconductor structures with enhanced performance at decreased dimensions. Particularly desirable are field effect devices, such as field effect transistors, fabricated with decreased dimensions and also having reduced short channel effects, without degradation of carrier motilities. Also desirable are related methods for fabricating the semiconductor structures with the foregoing enhanced performance characteristics at decreased dimensions.